As illustrated in FIG. 10, an active liquid crystal display device is constructed by sealing liquid crystals 2 in the space between a pair of upper and lower transparent glass substrates 1b and 1a.
As shown in FIG. 9, formed on the lower substrate 1a are scanning lines 31, 32 . . . , and signal lines 41, 42 . . . intersecting the scanning lines 31, 32 . . . at right angles. The scanning lines 31, 32 . . . are formed by a conducting film, and scanning signals from a scanning drive circuit K are successively applied to the scanning lines 31, 32 . . . On the other hand, the signal lines 41, 42 . . . are formed by a conducting film, and data signals from a data drive circuit L are successively applied to the signal lines 41, 42 . . .
Mounted in the vicinity of each of the intersections of the scanning lines 31, 32 . . . and the signal lines 41, 42 . . . are a thin film transistor (TFT) 5 as a switching element, and a pixel electrode 6 formed by a conducting film. The TFT 5 is electrically connected to both of the lines, and the pixel electrode 6 is connected to the TFT 5.
As shown in FIG. 10, a common electrode 7 and a color filter 8 are mounted on the upper glass substrate 1b. The common electrode 7 is formed by a transparent conducting film and connected to a common line 9 to which a common signal is applied. The pixel electrode 6 and the common electrode 7 form a capacitor 12 for ensuring a liquid crystal capacitance CLC as shown in FIG. 11.
As illustrated in FIG. 9, in the TFT 5, a gate electrode 5g is connected to each of the scanning lines 31, 32 . . . , a source electrode 5s is connected to each of the signal lines 41, 42 . . . , and a drain electrode 5d is connected to the pixel electrode 6.
Moreover, an additional capacitance line 10 formed by a conducting film is arranged below the pixel electrode 6, and connected to the common line 9. Considering an improvement of the data retentivity of the liquid crystals 2 to achieve high image quality, a capacitor 13 for ensuring an additional capacitance Cs is formed by the pixel electrode 6 and the additional capacitance line 10 as shown in FIG. 11.
In the liquid crystal display device of the above-mentioned structure, for example, when scanning signals are successively input downward from the scanning drive circuit K to the scanning lines 31, 32 . . . , the gates of a line of the TFTs 5 are simultaneously turned ON by the input of the scanning signals, and a display-use data signal is input for each pixel from the signal lines 41, 42 . . . by the data drive circuit L. As a result, the data signal is applied to the pixel electrode 6, and the transmittance of the liquid crystals 2 is changed by the potential difference between the pixel electrode 6 and the common electrode 7.
In this case, when a direct current continues to be supplied over a long time, the data retentivity of the liquid crystals 2 deteriorate. Therefore, the liquid crystals 2 are driven by a so-called AC drive method in which a positive voltage and a negative voltage are alternately applied to the pixel electrode 6 by switching the polarity of data signals to be input to the signal lines 41, 42 . . . for example, every horizontal period.
As the ideal capacitance (pixel capacitance) for a single pixel, in general, only the liquid crystal capacitance CLC and the additional capacitance Cs exist between the pixel electrode 6 and the common electrode 7 and between the pixel electrode 6 and the additional capacitance line 10, respectively, as shown in FIG. 11.
Actually, when conducting films are placed parallel to each other or conducting films are placed one upon another with an insulating film therebetween, a parasitic capacitance is generated between the conducting films. For example, as shown in FIG. 15, in a pixel located in the second row and the first column, i.e., a pixel in which the gate of the TFT 5 is connected to the second scanning line from the top, 32, and the source thereof is connected to the first signal line from the left, 41, the periphery of the pixel electrode 6 is enclosed by the upper and lower scanning lines 31 and 32, and the right and left signal lines 41 and 42 as shown in FIG. 9. Therefore, as illustrated in FIG. 12, parasitic capacitances Cgd2, Cgd1, Csd2 and Csd1 are generated between the pixel electrode 6 and the lines 31, 32, 41, 42, respectively.
The parasitic capacitance ratio in this pixel is given byα=ΔC/(CLC+Cs+ΔC)  (1)where ΔC=Cgd1+Cgd2.
When driving the liquid crystals 2 by the above-mentioned AC drive method, such a parasitic capacitance ratio α affects the fluctuation ΔV of a voltage applied to the pixel electrode 6, and the voltage fluctuation ΔV generates a DC component, resulting in deterioration of the data retentivity. In order to prevent the generation of the DC component, in prior arts, optimization is performed for each gray scale according to the parasitic capacitance ratio α.
The above explanation of the parasitic capacitance generated in each pixel is given for a pixel whose TFT 5 is connected to the scanning line 32 located in the second row from the top.
Next, with reference to a pixel whose TFT 5 is connected to the topmost scanning line 31 from which the scanning of scanning signal is initiated, the following description will explain a parasitic capacitance generated in this pixel. Since no scanning line is present above the pixel electrode 6 constituting this pixel, the parasitic capacitance Cgd2 is not generated.
Therefore, in this case, the parasitic capacitance ratio is given byα′=ΔC/(CLC+Cs+ΔC′)  (2)where ΔC′=Cgd1.
Namely, the parasitic capacitance ratio in the pixels corresponding the scanning lines 32, 33 . . . other than topmost scanning line 31 becomes the parasitic capacitance ratio α given by Equation (1) because these scanning lines are all symmetrically arranged about the additional capacitance line 10 as shown in FIG. 9. However, since the topmost scanning line 31 is not symmetrical about the additional capacitance line 10, the parasitic capacitance ratio in the pixels corresponding to the topmost scanning lines 31 becomes the parasitic capacitance α′ given by Equation (2).
Thus, the parasitic capacitance ratio in the pixels corresponding to the topmost scanning line 31 differs from the parasitic capacitance ratio in the pixels corresponding to the scanning lines 32, 33 . . . located after the first row.
As described above, optimization is performed for the pixels corresponding to the scanning lines 32, 33 . . . after the first row so as to reduce the influence of the parasitic capacitance ratio α and prevent the application of a DC component to the liquid crystals 2.
However, since the parasitic capacitance ratio α′ in the pixels corresponding to the topmost scanning line 31 differs from the parasitic capacitance ratio in the pixels corresponding to other scanning lines, the fluctuation ΔV of the voltage to be applied to the pixel electrodes 6 cannot be eliminated. As a result, an extremely small DC component is applied to the liquid crystals 2 in the pixels corresponding to the first scanning line 31, and therefore the data retentivity of the liquid crystals 2 deteriorate with time.
Consequently, a line of pixels corresponding to the topmost scanning lines 31 may cause a defect, for example, a bright line, deteriorating the display quality. In this case, for example, if the liquid crystals 2 are of normally white type, a bright line appears in the halftone display. On the other hand, if the liquid crystals 2 are of normally black type, a black line appears in the halftone display. Such a phenomenon is particularly noticeable when a current is supplied under high temperatures.